1. Technical Field
The present disclosure relates to data processing systems, and particularly systems which can simultaneously or time-share execute several applications, embedded systems and systems integrated onto a chip. The present disclosure also relates to systems having one or more central processing units linked to one or more peripheral units, and the access to the peripheral units.
2. Description of the Related Art
FIG. 1 schematically represents the architecture of a data processing system PS1. The system PS1 comprises a physical central processing unit CPU, and a peripheral unit PRP1 connected to the unit CPU, by means of an address and data bus for example. The peripheral unit PRP1 may for example be a unit for interfacing with external memories, an input/output port, for example of USB (Universal Serial Bus) or UART (Universal Asynchronous Receiver Transmitter) type, or even a DMA (Direct Memory Access) control unit.
The unit CPU can time-share execute several independent applications or operating systems CP1, CP2, CP3, CP4, referred to below as “virtual processing unit”. Generally, a “virtual processing unit” means a software component capable of working in a native and autonomous manner on one or more processors. The unit CPU executes a trust agent TA1 which acts as a “hypervisor” to enable the execution of several virtual units or sessions, for example in a virtualization context. The agent TA1 thus manages the activation and the deactivation of the virtual units, for example depending on their priority levels and rights to access the resources of the system.
The peripheral unit PRP1 comprises a control interface PINT comprising one or more input and/or output and/or input/output registers RG1-RG4, and a peripheral processing unit PRE. The interface PINT is accessible via an access point EP corresponding to one or more addresses of the space addressable by the unit CPU.
The registers RG1-RG4 can each have an address of the addressable space. Thus, the units CP1-CP4 can selectively read and/or write-access each of the registers RG1-RG4.